Page 121 - 《应用声学》2024年第6期
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第 43 卷 第 6 期 Vol. 43, No. 6
2024 年 11 月 Journal of Applied Acoustics November, 2024
⋄ 研究报告 ⋄
基于架桥套刻改进声表面波芯片探测工艺研究
王 君 † 孟腾飞 于海洋 王永安 倪 烨 袁 燕 张 倩
(北京航天微电科技有限公司 北京 100854)
摘要：为避免芯片尺寸封装工艺中金属凸点过多，实现声表面波芯片的片上测试，提高良品率，该文研究利用
架桥套刻的工艺制备声表面波芯片。在叉指图层上制备绝缘桥墩，在绝缘桥墩上制备连通内部电极和外部电
极的导电桥，通过绝缘桥墩将导电桥与汇流条隔开，实现内部电极的引出。通过实验验证方案的可行性，利用
传统光刻技术在衬底上制备叉指图层，利用套刻对准技术制备覆盖在汇流条上的聚酰胺酸绝缘桥墩，并在绝
缘桥墩上制备连接内部电极和外部电极的导电桥，得到 SAW 芯片。通过探针点测直接片上测试芯片性能，测
试结果达到预期要求。
关键词：声表面波芯片；绝缘桥墩；架桥套刻；芯片尺寸封装
中图法分类号: TN713 文献标识码: A 文章编号: 1000-310X(2024)06-1297-05
DOI: 10.11684/j.issn.1000-310X.2024.06.012
Research on improving the detection of surface acoustic wave chip by
alignment and bridging technology
WANG Jun MENG Tengfei YU Haiyang WANG Yong’an NI Ye
YUAN Yan ZHANG Qian
(Beijing Aerospace Micro-Electronics Technology Co., Ltd., Beijing 100854, China)
Abstract: In this paper, an approach of alignment and bridging to address excessive metal bumps in the chip
size package (CSP) process is proposed, aiming to produce surface acoustic wave (SAW) chips with improved
on-chip testing capabilities and yield. The proposed method involves the use of an interdigitated layer with an
insulating bump that includes a conductive sheet connecting the internal and external electrodes. By separating
the conductive sheet and the bus bar through the insulating bump, the internal electrode can be extracted
successfully. To verify the feasibility of the approach, experiments are conducted as well. The interdigitated
layer is prepared on the substrate using conventional photolithography technology. A polyamic acid insulating
bump, covering the bus bar, is generated through engraving alignment techniques. Subsequently, a conductive
sheet is assembled on the insulating bump, connecting the internal and external electrodes, resulting in the
fabrication of SAW chips. Direct probe point measurements are carried out to evaluate the performance of the
SAW chip, and the obtained results successfully meet the expected requirements.
Keywords: The surface acoustic wave chip; The insulating bump; Alignment and bridging; Chip size packing
2023-08-14 收稿; 2023-09-13 定稿
作者简介: 王君 (1992– ), 女, 河北唐山人, 硕士, 研究方向: 半导体先进封装技术。
† 通信作者 E-mail: wjwjun@126.com
